1. Field of the Invention
The present invention relates to a routing method. More particularly, the present invention relates to a method for dynamically allocating interrupt pins.
2. Description of Related Art
An interrupt request (IRQ) is used to inform and request a processor to suspend when an apparatus performs a specific action, so as to execute a corresponding calculation. The IRQ is sent via so-called interrupt lines, and the number of the interrupt lines varies depending on an interrupt controller adopted by a mainboard. A conventional computer uses a programmable interrupt controller (PIC) having 16 interrupt lines. However, these interrupt lines are still far from enough for computers with increasingly advancing functions and I/O devices. Most of the interrupt lines are occupied and even shared by several hardware devices. Therefore, some new mainboards adopt an advanced programmable interrupt controller (APIC) for managing over 32 IRQs which can be used by more hardware apparatuses while avoiding the share of interrupt lines.
A mainboard adopting PIC usually only has four available interrupt lines for a PCI bus to use. In another aspect, a new mainboard adopting APIC has eight available interrupt lines. Consequently, although there are six PCI slots on the mainboard, they can only use these four or eight IRQs. Moreover, accelerated graphics port (AGP), universal serial bus (USB), redundant array of independent disks (RAID) controller, and some on-board local area network (LAN) interfaces, 1394 interface, and serial ATA (SATA) interface all should utilize IRQs. Thus, it is inevitable that several PCI slots share one IRQ.
FIG. 1 shows a hardware configuration of a conventional PIC/IOAPIC mainboard. Referring to FIG. 1, a conventional PIC mainboard is configured to have a CPU 110, a north bridge chip 120, a south bridge chip 130, and four PCI slots 140, 150, 160, 170. The PCI slots 140, 150, 160, and 170 respectively transmit four interrupt messages INTA/INTB/INTC/INTD to interrupt routing registers Rx_A, Rx_B, Rx_C, Rx_D (x=1, 2, 3, 4) on the north bridge chip 120. As the PIC mainboard only supports four IRQs, the PCI slots 140, 150, 160, and 170 share four interrupt lines to send out interrupt messages while the north bridge chip 120 actually transmits the interrupt messages to the south bridge chip 130. The south bridge chip 130 receives the interrupt messages transmitted by the north bridge chip 120 with four interrupt router registers RA, RB, RC, RD respectively. These interrupt messages are then transmitted to a PIC (8259 PIC), and the 8259 PIC forwards an IRQ to the CPU 110. It should be noted that the conventional IOAPIC mainboard has an extra IOAPIC as compared with the PIC mainboard, and meanwhile forwards an IRQ to the CPU 110 by the use of the 8259 PIC and IOAPIC.
FIG. 2 is a conventional routing configuration table of interrupt pins. Referring to FIG. 2, pins A, B, C, D of each PCI slot are corresponding to different interrupt messages INTA/INTB/INTC/INTD, and a basic input/output system (BIOS) is also corresponding to different interrupt messages INTA/INTB/INTC/INTD when executing a power-on self test (POST), so as to configure the used/shared IRQs. For example, the pins A, B, C, D of Slot #2 are corresponding to the interrupt messages INTD/INTA/INTB/INTC. Therefore, during the configuration of the IRQs, numerals 4, 1, 2, 3 are stored in the corresponding interrupt routing registers Rx_D, Rx_A, Rx_B, Rx_C (x=1, 2, 3, 4) in sequence.
If a PCI interface card is inserted in each of the above four PCI slots, and each PCI interface card must triggers four interrupts from interrupt pins 1, 2, 3, 4 respectively, each IOAPIC interrupt line is shared by four hardware apparatuses, and the number of the drivers of the hardware apparatus serially linked on the four interrupt lines are four. Therefore, under such circumstance, each IOAPIC interrupt line is shared in the same way, which is the optimal situation.
However, if a PCI interface card is inserted in each of the four PCI slots, and each PCI interface card must use the interrupt pins as shown in FIG. 3, the problem of nonuniform allocation of interrupt pins may occur. For example, the interrupt pin A is shared by four PCI slots, but the interrupt pin D is only used by one PCI slot. At this time, the allocation of the IOAPIC interrupt line is not optimal, which may result in a situation that some interrupt pins are busily engaged while some others are quite free. Therefore, such situation has much room for improvement.